The Peripheral Component Interface (PCI) bus was developed as a high speed I/O bus alternative to the Industry Standard Architecture (ISA) I/O bus commonly used in IBM PC-compatible personal computer systems. The I/O bus links peripherals, including disk drives, video screens, network cards, to a host bus, where the host bus links the central processor unit and the memory, usually random access memory. Due to its higher information handling rate than the ISA bus, the PCI bus is particularly useful in situations where there are large amounts of data to be transferred, such as Super VGA images and graphically based operating systems like WINDOWS.RTM.. The PCI bus has a clock rate of 33 MHz and uses a 32 bit word, in contrast to the 16 bit word of the ISA which operates at 8 MHz. Thus, the data handling capabilities of the PCI bus are significantly improved over the ISA bus.
As computer applications become increasingly more sophisticated, and video screens increase in resolution, the data throughput of computers continues to increase. It is therefore important to accommodate this increase in the context of data throughput in I/O buses which interface with computers.
One area of concern in limiting the data throughput of a PCI bus system is the bridge spanning between two PCI buses. Commonly, a PCI-to-PCI bridge includes a first-in-first-out register which receives information from a first PCI bus and passes the information over to the second PCI bus. There are various handshake, verification and data transfer procedures which all take time to complete, and which slow down the transfer of data from one bridge to another.
Throughput across bussing architectures becomes particularly important where large blocks of data are to be transferred to a requesting device from a device targeted for supplying the data. Furthermore, it would be advantageous to provide the ability for commands to be retried or reissued at the request of the target device and the initiating device when necessary. Therefore, it would be desirable for a system to provide for the direct transfer of blocks of data across computer buses while taking into account the desirability of implementing initiating device reissue commands and target device retry commands. The present invention provides an arrangement which overcomes the aforementioned drawbacks, and offers other advantages over the prior art.